Current methods of performance based binning of integrated circuits rely on test structures placed in various positions in the integrated circuit. This method can often misrepresent the bin because the results can often be placement dependent and not represent the actual performance of circuits in positions different from those of the test structures. The result is often power usage higher then predicted from the assigned bin or performance lower than expected from the assigned bin. Accordingly, there exists a need in the art to mitigate the deficiencies and limitations described hereinabove.